1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and, in particular, to the formation of a tungsten-based interconnect structure involving the deposition of a thin conductive barrier layer in a high aspect ratio opening.
2. Description of the Related Art
During the process of manufacturing sophisticated semiconductor devices, such as modern CPUs, a plurality of different material layers are deposited on each other and patterned to define required device features. In general, subsequent material layers should exhibit good adhesion to each other while at the same time maintaining the integrity of each individual layer, i.e., chemical reaction of adjacent layers and/or diffusion of atoms from one layer into the other layer should be avoided during the manufacturing processes for the fabrication of the individual layers and subsequent processes as well as afterwards when operating the completed device. To meet these requirements, an intermediate layer is often required to provide good adhesion and to suppress diffusion and thus undue interference between neighboring materials during processing and operation. A typical example of this in the fabrication of semiconductor devices is the formation of interconnect plugs, wherein openings and trenches having a bottom region and a sidewall region have to be provided with a corresponding intermediate layer, that is a conductive barrier layer, so that a subsequently deposited conductive material exhibits good adhesion to the surrounding dielectric layer, and undue interaction during processing and operation may be avoided. In advanced semiconductor devices, the interconnect plugs are typically formed of a tungsten-based metal and are provided in an interlayer dielectric stack which is typically comprised of silicon dioxide, including a bottom etch stop layer typically formed of silicon nitride.
In general, the electrical resistance of the barrier metal layer is significantly higher than the resistance of the tungsten-based material forming the contact plug, so that the thickness of the barrier metal layer is selected to be as small as possible in order to avoid unduly increasing the overall resistance of the contact plug.
In modern integrated circuits, openings (so-called vias) are formed exhibiting an aspect ratio that may be as high as approximately 8:1 or more, and the opening may have a diameter of 0.1 μm or smaller. The aspect ratio of such openings is generally defined as the ratio of the depth of the opening to the width of the opening. Accordingly, it is extremely difficult to form a thin, uniform barrier metal layer on the entire sidewalls, especially at the bottom corners, to effectively avoid direct contact of the metal with the surrounding dielectric material, i.e., it is difficult to form a barrier metal layer that adequately covers all surfaces of the openings.
With reference to FIG. 1, a typical conventional process for manufacturing contacts to a circuit device in accordance with a well-established tungsten technology will now be described in more detail in order to illustrate the problems involved in the formation of a reliable conductive barrier layer.
FIG. 1 schematically shows a semiconductor device 100 during a manufacturing stage for the formation of interconnect plugs providing a connection to a circuit element, such as a transistor 110, that is formed above an appropriate semiconductor substrate 101. The circuit element 110 may comprise one or more contact regions, such as a gate electrode 111 and drain and source regions 112. The circuit element 110 is covered by a dielectric material, which may comprise a contact etch stop layer 102, which may be formed of silicon nitride, and an interlayer dielectric material 103, which is typically silicon dioxide. Moreover, two contact openings 104a, 104b are formed within the dielectric layers 103 and 102 so as to connect to the respective contact regions 111 and 112. Furthermore, a conductive barrier layer, which is typically comprised of a titanium liner 105 and a titanium nitride layer 106 in tungsten contact technology, is formed on the dielectric layer 103 and within the contact openings 104a, 104b. The titanium liner 105 and the titanium nitride barrier layer 106 may be formed so as to enhance the reliability of the subsequent deposition of a tungsten-based material, wherein the deposition process is typically performed as a chemical vapor deposition (CVD) process, in which tungsten hexafluorine (WF6) is reduced in a thermally activated first step on the basis of silane (SiH4) and is then, in a second step, converted into tungsten on the basis of hydrogen. During the reduction of the tungsten on the basis of silane, a direct contact to the silicon dioxide of the dielectric layer 103 is substantially prevented by the barrier layer 106 in order to avoid undue silicon consumption from the silicon dioxide. However, titanium nitride exhibits a rather poor adhesion to silicon dioxide and may therefore jeopardize the reliability of the respective tungsten plug formed subsequently. Consequently, the titanium liner 105 is provided for improving adhesion of the barrier layer 106.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1 may comprise the following processes. After the formation of the circuit element 110 on the basis of well-established manufacturing techniques, the contact etch stop layer 102 may be formed on the basis of well-known plasma enhanced chemical vapor deposition (PECVD) techniques, followed by the deposition of the silicon dioxide of the layer 103 on the basis of TEOS, thereby providing a dense and compact material layer. After any optional planarization processes for planarizing the layer 103, a photolithography sequence may be performed on the basis of well-established recipes, followed by anisotropic etch techniques for forming the contact openings 104a, 104b in the layer 103, wherein the etch process may reliably be controlled on the basis of the etch stop layer 102. Thereafter, a further etch process may be performed to finally open the contact etch stop layer 102 on the basis of well-established techniques. Thereafter, the titanium liner 105 may be formed on the basis of ionized physical vapor deposition, such as sputter deposition. The term “sputtering” or “sputter deposition” describes a mechanism in which atoms are ejected from a surface of a target material upon being hit by sufficiently energetic particles. Sputtering has become a dominant technique for depositing titanium, titanium nitride and the like. Although, in principle, an improved step coverage could be obtained by using CVD techniques, sputter deposition is widely used for the deposition of the liner 105 for the following reasons.
Sputter deposition allows the relatively uniform deposition of layers over large area substrates, since sputtering can be accomplished from large-area targets. Control of film thickness by sputter deposition is relatively simple as compared to CVD deposition and may be achieved by selecting a constant set of operating conditions, wherein the deposition time is then adjusted to achieve the required film thickness. Moreover, the composition of compounds, such as titanium nitride used in the barrier layer 106, can be controlled more easily and precisely in sputter deposition processes as compared to CVD. Additionally, the surfaces of the substrates to be processed may be sputter-cleaned prior to the actual film deposition so that any contamination of the surface may be efficiently removed and further re-contamination prior to the actual deposition process may be effectively suppressed. For an efficient deposition of a moderately thin material within the contact openings 104a, 104b having a moderately high aspect ratio, so-called ionized sputter deposition techniques are used, in which target atoms liberated from the target are efficiently ionized by a respective plasma ambient while moving towards the substrate. On the basis of a DC or RF bias, the directionality of the moving ionized target atoms may be significantly enhanced, thereby enabling the deposition of target material at the bottom of the contact openings 104a, 104b even for high aspect ratios.
Due to this mechanism, however, the layer thickness at the bottom 104c may be significantly thicker compared to a thickness at the sidewalls of the contact openings 104a, 104b, even though these sidewalls may be covered by a substantially continuous layer. In particular, at lower sidewall portions 104d, the corresponding layer thickness may be significantly thinner compared to the thickness at the bottom 104c. However, a reliable and thus minimum layer thickness may be required, especially at the bottom sidewall portions 104d, in order to substantially prevent any deleterious interaction during the subsequent tungsten deposition. For example, for a minimum layer thickness of approximately 50-60 Å at the lower sidewall portions 104d, a bottom layer thickness of approximately 300-400 Å may be required, thereby resulting in an increased contact resistivity as the combination of titanium nitride and titanium exhibits a moderately high resistance compared to the contact regions 112 and the subsequently filled-in tungsten.
In view of the situation described above, there exists a need for an enhanced technique that enables the formation of a reliable titanium and titanium nitride barrier layer for tungsten-based contact technology while avoiding or at least reducing the effects of one or more of the problems identified above.